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FEATURES Complete Analog l/O Port for DSP-Based FAX/MODEM Applications Linear-Coded 16-Bit Sigma-Delta ADC Linear-Coded 16-Bit Sigma-Delta DAC On-Chip Anti-Alias and Anti-lmage Filters Digital Resampling/lnterpolation Filter 7.2 kHz, 8.0 kHz, and 9.6 kHz Sampling Rates 8/7 Mode for 8.23 kHz, 9.14 kHz, and 10.97 kHz Sampling Rates Synchronous and Asynchronous DAC/ADC Modes Bit and Baud Clock Generation Transmit Digital Phase-Locked Loop for Terminal Synchronization Independent Transmit and Receive Phase Adjustment Serial Interface to DSP Processors +5 V Operation with Power-Down Mode 28-Pin Plastic DlP/44-Lead PLCC/28-Lead SOIC APPLICATIONS High Performance DSP-Based Modems V.32ter, V.32bis, V.32, V.22bis, V.22, V.21, Bell 212A, 103 Fax and Cellular-Compatible Modems V.33, V.29, V.27ter, V.27bis, V.27, V.26bis Integrated Fax, Modem, and Speech Processing GENERAL DESCRIPTION
ANALOG INPUTS
PSTN Signal Port AD28msp01
FUNCTIONAL BLOCK DIAGRAM
16-BIT SIGMA-DELTA ADC DIGITAL DATA AND CONTROL SERIAL PORT
VOLTAGE REFERENCE
RESAMPLING INTERPOLATION FILTER
DIFFERENTIAL ANALOG OUTPUT
16-BIT SIGMA-DELTA DAC
CLOCK INPUTS CLOCK OUTPUTS
CLOCK GENERATION
The AD28msp01 is a complete analog front end for high performance DSP-based modems. The device includes all data conversion, filtering, and clock generation circuitry needed to implement an echo-cancelling modem with a single host digital signal processor. Software-programmable sample rates and clocking modes support all established modem standards. The AD28msp01 simplifies overall system design by requiring only +5 volts. The inclusion of on-chip anti-aliasing and anti-imaging filters and 16-bit sigma-delta ADC and DAC ensures a highly integrated and compact solution for FAX or data MODEM applications. Sigma-delta conversion technology eliminates the need for complex off-chip anti-aliasing filters and sample-and-hold circuitry. The AD28msp01 utilizes advanced sigma-delta technology to move the entire echo-cancelling modem implementation into the digital domain. The device maintains a -72 dB SNR throughout all filtering and data conversion. Purely DSP-based echo cancellation algorithms can thereby maintain robust bit error rates under worst-case signal attenuation and echo amplitude conditions. The AD28msp01's on-chip interpolation filter resamples the received signal after echo cancellation in the DSP, freeing the processor for other voice or data communications tasks. REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
On-chip bit and baud clock generation circuitry provides for either synchronous or asynchronous operation of the transmit (DAC) and receive (ADC) paths. Each path features independent phase advance and retard adjustments via software control. The AD28msp01 can also synchronize modem operation to an external terminal bit clock. The AD28msp01's serial I/O port provides an easy interface to host DSP microprocessors such as the ADSP-2101, ADSP-2105, and ADSP-2111. Packaged in a 28-pin plastic DIP, 44-lead PLCC, 44-pin TQFP, or 28-lead SOIC, the AD28msp01 provides a compact solution for space-constrained environments. The device operates from a +5 V supply and offers a low power sleep mode for battery-powered systems. A detailed block diagram of the AD28msp01 is shown in Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD28msp01
16-BIT SIGMA-DELTA ADC
VFB SDOFS VIN INPUT AMP ANALOG SIGMA-DELTA MODULATOR 1 DIGITAL DECIMATION FILTER 16 DIGITAL ANTI-ALIASING LOW-PASS FILTER 16 DIGITAL HIGH-PASS FILTER 16 SDO
1.728 MHz
28.8/32.0/38.4 kHz
7.2/8.0/9.6 kHz
7.2/8.0/9.6 kHz
500k
VOLTAGE REFERENCE
RESAMPLING INTERPOLATION FILTER
SCLK SERIAL PORT
16-BIT SIGMA-DELTA DAC
VOUT+ VOUT- OUTPUT DIFF. AMP ANALOG SMOOTHING FILTER 1 DIGITAL SIGMA-DELTA MODULATOR 16 DIGITAL INTERPOLATION FILTER 16 DIGITAL ANTI-IMAGING LOW-PASS FILTER 16 SDI
SDIFS 1.728 MHz INTERNAL CLOCK 1.728 MHz 28.8/32.0/38.4 kHz 7.2/8.0/9.6 kHz
TSYNC
CLOCK GENERATION
CONTROL CIRCUITRY AND SEQUENCER
CONTROL REGISTERS
tCONV tBAUD
tBIT
rCONV rBAUD
rBIT
MCLK
RESET
CS
Figure 1. AD28msp01 Block Diagram
PIN DESCRIPTIONS
Name
Type Description
Name SDOFS
Type Description O/Z Framing synchronization signal for serial data transfers from the AD28msp01 (via the SDO pin). This pin is 3-stated when CS is low.
Analog Interface VIN I Analog input to the inverting terminal of the input amplifier. VFB O Feedback terminal of the input amplifier. VOUTP O Analog output from the noninverting terminal of the output differential amplifier. VOUTN O Analog output from inverting terminal of the output differential amplifier. Serial Interface SCLK O/Z Serial clock used for clocking data or control bits to/from the serial port (SPORT). The frequency of this clock is 1.7280 MHz. This pin is 3-stated when the CS is low. SDI I Serial data input of the SPORT. Both data and control information are input on this pin. This pin is ignored when CS is low. SDO O/Z Serial data output of the SPORT. Both data and control information are output on this pin. This pin is 3-stated when CS is low. SDIFS I Framing synchronization signal for serial data transfers to the AD28msp01 (via the SDI pin). This pin is ignored when CS is low.
Clock Generation TSYNC I Transmit synchronization clock. This signal is used to synchronize the transmit clocks and the converter clocks to an external terminal/ bit-rate clock. It is used in the V.32 TSYNC and Asynchronous TSYNC modes and is ignored in other operating modes. The frequency of the external clock must be programmed in Control Register 0. This pin must be tied high or low if it is not being used. TBIT O Transmit bit rate clock. This is an output clock whose frequency is programmable via Control Register 3. It is synchronized with the TCONV clock. TBAUD O Transmit baud rate clock. This is an output clock whose frequency is programmable via Control Register 3. It is synchronized with the TCONV clock.
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REV. A
AD28msp01
PIN DESCRIPTIONS (Continued) FUNCTIONAL DESCRIPTION A/D Conversion
Name
Type Description Transmit conversion clock. This clock indicates when the ADC has finished a sampling cycle. The frequency of TCONV is programmed by setting the sample rate field in Control Register 0. The programmed TCONV rate can be scaled by a factor of 8/7 by setting Bit 9 in Control Register 1. The phase of TCONV can be adjusted by writing the Transmit Phase Adjust Register (Control Register 5). Receive bit rate clock. This is an output clock whose frequency is programmable via Control Register 2. It is synchronized with the RCONV clock. Receive baud rate clock. This is an output clock whose frequency is programmable via Control Register 2. It is synchronized with the RCONV clock. Receive conversion clock. This clock indicates when the DAC has finished a sampling cycle. The frequency of RCONV is programmed by setting the sample rate field in Control Register 0. The programmed RCONV rate can be scaled by a factor of 8/7 by setting Bit 9 in Control Register 1. The phase of RCONV can be adjusted by writing the Receive Phase Adjust Register (Control Register 4).
TCONV O
The A/D conversion circuitry of the AD28msp01 consists of an analog input amplifier and a sigma-delta analog-to-digital converter (ADC). The analog input signal to the AD28msp01 must be ac coupled.
Analog Input Amplifier
The analog input amplifier is internally biased by an on-chip voltage reference in order to allow operation of the AD28msp01 with a +5 V power supply. Input signal level to the sigma-delta modulator should not exceed VINMAX, which is specified under "Analog Interface Electrical Characteristics." Refer to "Analog Input" in the "Design Considerations" section of this data sheet for more information.
ADC
RBIT
O
RBAUD O
RCONV O
The ADC consists of a 3rd-order analog sigma-delta modulator, a decimation filter, an anti-aliasing low-pass filter, and a highpass filter. The analog input is applied to the input amplifier. The output of this amplifier is applied to an analog sigma-delta modulator which noise-shapes it and produces 1-bit samples at a 1.7280 MHz rate. This bit stream is fed to the decimation filter, which increases the resolution to 16-bits and decreases the sampling frequency. The parallel data stream is then processed by the anti-aliasing low-pass filter which further reduces the sampling rate. Finally, the high-pass filter removes input frequency components at the low end of the spectrum. Either the high-pass filter alone or the high-pass/anti-aliasing low-pass filter combination can be bypassed by setting the appropriate bits in Control Register 1, thus producing samples at 7.2/8.0/9.6 kHz or 28.8/32.0/38.4 kHz, respectively. The gain and the frequency response of the AD28msp01 are altered when these filters are bypassed. The DSP processor that receives samples from the AD28msp01 may need to compensate for this change.
Decimation Filter
Miscellaneous MCLK I AD28msp01 master clock input. The frequency of this clock must be 13.824 MHz to guarantee listed specifications. RESET I Active-low chip reset. This signal sets all AD28msp01 control registers to their default values and clears the device's digital filters. SPORT output pins are 3-stated when RESET is low. SPORT input pins are ignored when RESET is low. CS I Active-high chip select. This signal 3-states all SPORT output pins and forces the AD28msp01 to ignore all SPORT input pins. If CS is deasserted during a serial data transfer, the 16-bit word being transmitted is lost. Power Supplies VCC Analog supply voltage (nominally +5 V) GNDA Analog ground VDD Digital supply voltage (nominally +5 V) GNDD Digital ground
The decimation filter is a sinc4 digital filter that increases resolution to 16 bits and reduces the sample rate to 28.8, 32.0, or 38.4 kHz (depending on the input sample rate). The 16 bit, parallel data stream output of the decimation filter is then processed by the anti-aliasing low-pass filter.
Anti-Aliasing Low-Pass Filter
The anti-aliasing low-pass filter further reduces the sampling rate by a factor of four to 7.2 kHz, 8.0 kHz, or 9.6 kHz (depending on the output sample rate of the decimation filter). The output is fed to the high-pass filter. The low-pass/high-pass filter combination can be bypassed by setting the appropriate bits in Control Register 1. If the filters are bypassed, the signal must be scaled by the following multipliers to achieve normal levels: 2.046 for 9.6 kHz, 0.987 for 8.0 kHz, and 0.647 for 7.2 kHz. When the filters are bypassed, the host DSP must be able to receive data at the 28.8/32.0/38.4 kHz rates. In this case, resampling interpolation should be disabled because of insufficient bandwidth to transmit both ADC and resampled data to the SPORT.
High-Pass Filter
The digital high-pass filter removes frequency components at the low end of the spectrum. The high pass filter can be bypassed by setting the appropriate bits in Control Register 1.
REV. A
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AD28msp01
The output of the ADC is transferred to the AD28msp01's serial port (SPORT) for transmission to the host DSP processor.
D/A CONVERSION
amplifier. Refer to "Analog Output" in the "Design Considerations" section of this data sheet for more information. The VOUTP and VOUTN outputs must be used as differential outputs; do not use either as a single-ended output.
SERIAL PORT
The D/A conversion circuitry of the AD28msp01 consists of a sigma-delta digital-to-analog converter (DAC) and a differential output amplifier.
DAC
The DAC consists of an anti-imaging low-pass filter, an interpolation filter, a digital sigma-delta modulator, and an analog smoothing filter. These filters have the same characteristics as the ADC's anti-aliasing filter and decimation filter. The DAC receives 16-bit samples from the host DSP processor via AD28msp01's SPORT. If the host processor fails to write a new value to the serial port, the existing (previous) data is read again. The data stream is filtered first by the DAC's antiimaging low-pass filter and then by the interpolation filter. The output of the interpolation filter is fed to the DAC's digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples. The output of the sigma-delta modulator is fed to the AD28msp01's analog smoothing filter where it is converted into a low-pass filtered, analog voltage.
Anti-lmaging Low-Pass Filter
The AD28msp01 includes a full-duplex synchronous serial port (SPORT) used to communicate with a host processor. The SPORT is used to read and write all data and control registers in the AD28msp01. The SPORT transfers 16-bit words, MSB first, at a serial clock rate of 1.7280 MHz. When the AD28msp01 exits reset, both the analog circuitry and the digital circuitry are powered down. The serial port will not transmit data to the host until the host sets the digital powerdown bit (PWDD) to 1 in Control Register 1. All control registers should be initialized before this bit is set. The SPORT is configured for an externally generated receive frame sync (SDIFS), an internally generated serial clock (SCLK), and an internally generated transmit frame sync (SDOFS). The host processor should be configured for an external serial clock and receive frame sync and an internal transmit frame sync.
DSP Processor Interface
The anti-imaging low-pass filter filters the 7.2 kHz, 8.0 kHz, or 9.6 kHz data stream form the SPORTs, and raises the sampling rate to 28.8 kHz, 32.0 kHz, or 38.4 kHz. The anti-imaging low-pass filter can be bypassed by setting the appropriate bit in Control Register 1. This results in a gain change. If the filter is bypassed, the signal must be scaled by the following multipliers to achieve normal levels: 2.046 for 9.6 kHz, 0.987 for 8.0 kHz, and 0.647 for 7.2 kHz. When the filter is bypassed, the host DSP must be able to transmit data at the 28.8/32.0/38.4 kHz rates. In this case, resampling interpolation should be disabled because of insufficient bandwidth to transmit both ADC and resampled data to the SPORT.
Interpolation Filter
The AD28msp01-to-host processor interface is shown in Figure 2.
AD28msp01
SDO SDOFS SCLK CS SDI SDIFS
DSP PROCESSOR
SERIAL DATA RECEIVE RECEIVE FRAME SYNC SERIAL CLOCK FLAG SERIAL DATA TRANSMIT TRANSMIT FRAME SYNC
Figure 2. AD28msp01-to-DSP Processor Interface
The AD28msp01's chip select (CS) must be held high to enable SPORT operation. CS can be used to 3-state the SPORT pins and disable communication with the host processor. To use the ADSP-2101 or ADSP-2111 as host DSP processor for the AD28msp01, refer to Figure 3. Note that the ADSP-2101's SPORT0 communicates with the AD28msp01's SPORT while the ADSP-2101's Flag Output (FO) is used to signal the AD28msp01's CS input. SPORT1 on the ADSP-2101 must be configured for flags and interrupts in this system.
AD28msp01
SDO SDOFS SCLK CS SDI SDIFS DR0 RFS0 SCLK0 FO DT0 TFS0
The interpolation filter contains is a sinc4 digital filter which raises the sampling rate to 1.7280 MHz by interpolating between the samples. These 16-bit samples are then processed by the digital sigma-delta modulator which noise-shapes the data stream and reduces the sample width to a single bit stream.
Analog Smoothing Filter
The AD28msp01's analog smoothing filter consists of a 2ndorder Sallen-Key continuous-time filter and a 3rd-order switched capacitor filter. The Sallen-Key filter has a 3 dB point at approximately 80 kHz. The analog smoothing filter converts the 1.7280 MHz bit stream output of the sigma-delta modulator into a low-pass filtered, differential analog signal.
Differential Output Amplifier
ADSP-2101
The differential output amplifier produces the AD28msp01's analog output (VOUTP, VOUTN). It can drive loads of 2 k or greater and has a maximum differential output voltage swing of 6.312 V peak-to-peak. The output signal is dc biased to the AD28msp01's on-chip voltage reference (2.5 V nominal) and can be ac coupled directly to a load or dc coupled to an external
Figure 3. AD28msp01-to-ADSP-2101 Interface
Figure 4 shows an ADSP-2101 assembly language program that initializes the AD28msp01 and implements a digital loopback through the processor.
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REV. A
AD28msp01
{This ADSP-2101 program initializes the AD28msp01} {and executes a loopback, or talk-through, routine.} . MODULE/RAM/BOOT = 0 MSP01; . VAR/DM/CIRC rec[2]; . VAR/DM/CIRC trans[2]; rset: irq2v: sprt0t: sprt0r: sprt1t: sprt1r: timerv: start: I2 = ^re c ; L2 = %rec; I3 = ^trans; L3 = %trans; M0 = 0; M1 = 1; S1 = 0; DM(0x3000) = SI; init dsp: AX0 = 0x2a0f; DM(0x3ff6) = AX0; AX0 = 0x101f; DM(0x3fff) = AX0; init msp01: IMASK = 0x10; AR = 0; CNTR = 6; DO initi UNTIL CE; TX0 = AR; IDLE; TX0 = SI; IDLE; AY0 = AR; AR = AY0 +1; AX1 = 1; AR = 0x18; TX0 = AX1; IDLE; TX0 = AR; AR = B#0025; DM(0x3ff3) = AR; IMASK = 0x18; JUMP wait; {Ext RFS, Int TfS, Ext SCLK, SLEN = 15} {SPORT0 control register} {Enable SPORT0} {System control register} {Initialize AD28msp01 control register} {Note: This section could be autobuffered.} {Enable SPORT0 TX interrupt} JUMP start; RTI; RTI; RTI; RTI; RTI; RTI; RTI; AX0 = 0x25; DM(0x3ff3) = AX0; RTI; RTI; JUMP receive; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; RTI; {Initialize DAGs} {Receive word buffer} {Transmit word buffer} {lnterrupt Vectors}
{Disable TX autobuffer}
{Reset the AD28msp01} {Initialize the ADSP-2101}
{Transmit address} {Transmit control word}
initi:
{Increment address} {Power up AD28msp01}
wait: receive:
{Enable RX autobuffering with I2, M1} {Autobuffer control register} {Enable RX and TX interrupt} {Wait for receive interrupt} {Receive Interrupt Routine}
DM(0x3ff3) = SI; AX1= DM(I2, M1); REV. A -5-
{Disable autobuffering} {Read first receive word from buffer}
AD28msp01
AX0 = DM(I2, M1); AY0 = 8; AR = AX1 - AY0; IF EQ JUMP goodstuff; RTI; goodstuff; MODIFY (I3, M1); DM(I3, M0) = AX0; MX1 = 6; AR = 0x06a7; DM(0x3ff3) = AR; TX0 = MX1; RTI; .ENDMOD;
Figure 4. AD28msp01 Initialization and ADSP-2101 Loopback Routine
Serial Data Output
{Read data word} {Verify AD28msp01 address = 8}
{Point to second word of TX buffer} {Load address word into MX1} {Enable TX and RX autobuffer} {Write to SPORT control Register} {Autobuffer start}
When the digital power-down bit (PWDD) of Control Register 1 is set to 1, the AD28msp01's SPORT begins transmitting data to the host processor. All transfers between the host processor and the AD28msp01 consist of a serial data output frame sync (SDOFS) followed by a 16-bit address word, then a second frame sync followed by a 16-bit data word. Address/data word pairs are transmitted whenever they become available. The ADC takes precedence over the Interpolator output data. If a new word becomes available while a serial transfer is in progress, the current serial transfer is completed before the new word starts transmission.
Serial Data Input
and receive timing as well as an additional clock signal for serial port timing. The receive clocks are the RCONV, RBIT and RBAUD signals. The individual clock rates are programmable and are all synchronized with RCONV. The transmit clocks are the TCONV, TBIT and TBAUD signals. The individual clock rates are programmable and are all synchronized with TCONV. Depending on the operating mode, the converter clocks can be synchronized to an external clock signal (TSYNC) or can be generated internally. The clocks can be adjusted in phase by setting the appropriate phase adjust register. All the AD28msp01 Bit/Baud clocks have a 50% duty cycle except the 1600 Hz baud rate. This baud rate has a 33%-66% duty cycle.
Resampling Interpolation Filter
The host processor must initiate data transfers to the AD28msp01 by asserting the serial data input frame sync (SDIFS) high. Each of the 16-bit address word and 16-bit data word transfers begins one serial clock cycle after SDIFS is asserted. The address word always precedes the data word. The second serial data input frame sync for the data word can be asserted as early as the last bit of the address word is transmitted, or any time after. The host processor must assert SDIFS shortly after the rising edge of SCLK and must maintain SDIFS high for one cycle because SDIFS is clocked by the SCLK falling edge. Data is then driven from the host processor shortly after the rising edge of the next SCLK and is clocked into the AD28msp01 on the falling edge of SCLK in that cycle. Each bit of a 16-bit address and 16-bit data word is thus clocked into the AD28msp01 on the falling edge of SCLK (MSB first). If SDIFS is asserted high again before the end of the present data word transfer, it is not recognized until the falling edge of SCLK in the last (LSB) cycle. When the serial port receives an interpolator or DAC input word, it writes the value to an internal register which is read by the AD28msp01 when it is needed. This allows the host to send data words at any time during the sample period. NOTE: Exact SPORT timing requirements are defined in the "Specifications" section of this data sheet.
Clock Generation
The resampling interpolation filter interpolates the data from the TCONV rate to 1.7280 MHz. The data is then resampled (decimated) in phase with the RCONV clock. The frequency response characteristics of the resampling interpolation filter are identical to the frequency response characteristics of the antiimaging, low-pass filter/interpolation filter combination. Figure 5 illustrates the effects of a resampling interpolation filter.
ANALOG SIGNAL SAMPLED AT 9600 Hz
OUTPUT OF INTERPOLATION FILTER
OUTPUT OF RESAMPLING FILTER
Figure 5. Effects of Interpolation Filter
The AD28msp01 generates all transmit and receive clocks necessary to implement standard voice-grade modems. The AD28msp01 can generate six different clock signals for transmit -6- REV. A
AD28msp01
Since the resample phase is locked to RCONV, it can be advanced or slipped by writing a signed-magnitude value to the Receive Phase Adjust Register (Control Register 2). The phase advance or slip is equal to the master clock period (13.824 MHz) multiplied by the signed-magnitude 9-bit value in Control Register 4. The change in phase requires a maximum of two RCONV cycles to complete. If the value written to Control Register 4 is less than the oversampling ratio, then the change will complete in one RCONV cycle.
Control Registers
the control register through the AD28msp01's serial port (SPORT). The control registers should be set up for the desired mode of operation before bringing the AD28msp01 out of power-down (by writing ones to the PWDA and PWDD bits in Control Register 1). The control registers are cleared (set to 0x0000) when the AD28msp01 is reset. The sampling rate should be set before writing ones to the power-down bits. Changing the sampling rate at any other time will force a soft reset. For more information about soft resets, refer to the end of this section of the data sheet. NOTE: Reserved bits should always be cleared to 0.
The AD28msp01's six control registers configure the device for various operating modes including filter bypass and powerdown. The AD28msp01's host processor can read and write to
Control Register 0 This register is used to:
address = 0x00
* Enable/disable the resampling interpolation filter * Set the external TSYNC clock rate * Select the sampling rate * Select the operating mode
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
INTEN
Interpolation filter enable 1 = enabled; 0 = disabled
OP2-0 TS3-0
TSYNC Rate (Hz) 0000 = 9600 0001 = 8000 0010 = 7200 0011 = 4800 0100 = 2400 0101 = 1200 0110 = 600 0111 = 19200 1000 = 14400 1001 = 12000 Operating Modes 000 = Asynchronous fallback mode 001 = Reserved 010 = Reserved 011 = Reserved 100 = V.32 TSYNC 101 = V.32 Internal Sync 110 = V.32 Loopback 111 = Async. fallback mode TSYNC
SR1-0
Sampling Rate (kHz) 00 = 9.6 01 = 8.0 10 = 7.2 11 = Reserved
Control Register 1 This register is used to:
address = 0x01
* Increase the sampling rate to 8/7 the rate selected in Control Register 0 * Power down the device * Bypass the digital filters
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2
FB2
1
FB1
0
FB0
0
0
0
SA87
When set to a 1, this bit increases the sampling rate to 8/7 of the programmed rate: (8/7) 9.6 kHz = 10.97 kHz, (8/7) 8.0 kHz = 9.14 kHz, (8/7) 7.2 kHz = 8.23 kHz
FB2-0
Filter Bypass Configuration FB2 FB1 FB0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
PWDA
Power Down Analog 1 = Standard Operation 0 = Low Power
PWDD
Power Down Digital 1 = Standard Operation 0 = Low Power
= = = = = = = =
No filter bypass (default) Reserved ADC Hi pass filter bypassed ADC Hi and Lo pass filter bypassed DAC filter bypassed Reserved DAC and ADC Hi pass filters bypassed DAC, ADC Hi and ADC Lo pass filters bypassed
REV. A
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AD28msp01
If any low-pass filter is bypassed, the resampling interpolation filter should be disabled (in Control Register 0.) Control Register 2 This register is used to: * Select the frequency of the Receive baud clock (RBAUD) * Select the frequency of the Receive bit clock (RBIT)
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
address = 0x02
BA2-0
Receive baud rate clock selection 000 = 2400 (default) 001 = 1600 010 = 1200 011 = 600 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved
BI3-0
Receive bit rate clock selection 0000 = 9600 (default) 0001 = 8000 0010 = 7200 0011 = 4800 0100 = 2400 0101 = 1200 0110 = 600 0111 = 19200 1000 = 14400 1001 = 12000 1010 = 19200 with SA87 in control register 1 set (not scaled by 8/7)
Control Register 3 This register is used to:
address = 0x03
* Select the frequency of the Transmit baud clock (TBAUD) * Select the frequency of the Transmit bit clock (TBIT)
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
BA2-0
Transmit baud rate clock selection 000 = 2400 (default) 001 = 1600 010 = 1200 011 = 600 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved
BI3-0
Transmit bit rate clock selection 0000 = 9600 (default) 0001 = 8000 0010 = 7200 0011 = 4800 0100 = 2400 0101 = 1200 0110 = 600 0111 = 19200 1000 = 14400 1001 = 12000 1010 = 19200 with SA87 in control register 1 set (not scaled by 8/7)
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AD28msp01
Control Register 4 address = 0x04 This register is the Receive Phase Adjust Register and it is used to: * Change the phase of the receive clocks (RBAUD, RBIT, RCONV)
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
0 - Phase advance 1 - Phase retard
P7-0
Phase Shift Magnitude The amount of time slipped or advanced is defined as this number represented by P7-P0 times the master clock period.
Once you have written a value to the register, subsequent writes are ignored until the register is finished incrementing/decrementing to zero. The phase advance or slip is equal to the master clock period (13.824 MHz) multiplied by the signed-magnitude 9-bit value in Control Register 4. The AD28msp01 decrements Control Register 4 as it adjusts the phase of RCONV. Control Register 4 will equal zero when the phase shift is complete. Control Register 5 address = 0x05 This register is the Transmit Phase Adjust Register and it is used to: * Change the phase of the Transmit clocks (TBAUD, TBIT, TCONV)
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
0 - Phase advance 1 - Phase retard
P7-0
Phase Shift Magnitude The amount of time slipped or advanced is defined as this number represented by P7-P0 times the master clock period.
This register must be equal to zero before its value can be changed. Once you have written a value to the register, subsequent writes are ignored until the register is finished incrementing/ decrementing to zero. The phase advance or slip is equal to the master clock period (13.824 MHz) multiplied by the signed-magnitude 9-bit value in Control Register 5. The AD28msp01 decrements Control Register 5 as it adjusts the phase of TCONV. Control Register 5 will equal zero when the phase shift is complete.
Soft Resets
Table I. Soft Reset
Bits Control Register 0, SR1-SR0 Control Register 0, OP2-OP0 Control Register 0, TS3-TS0 Control Register 1, FB2-FB0 Control Register 1, SA87
Data Registers
Configures Sampling rate Clock generation operating modes (async-to-V.32 or V.32-to-async) TSYNC rate Filter bypass configuration Sampling rate scaling by 8/7
Certain conditions cause the AD28msp01 to perform a soft reset; the DSP is reset but the control register values do not change. Table I shows when a soft reset is caused by changing the values of certain control register bits while the device is operating. When these bits are modified, the AD28msp01 will perform a soft reset and start up again in the new configuration. Reserved bits in the control registers should always be set to zero.
The AD28msp01 contains four data registers. Data Register 0 address = 0x06 DAC Input Register (write-only): The 16-bit twos complement values written to this register are input to the AD28msp01's digital-to-analog converter.
REV. A
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AD28msp01
Data Register 1 address = 0x07
Example
Interpolation Filter Input Register (write-only): The 16-bit twos complement values written to this register are input to the resampling interpolation filter. Data Register 2 address = 0x08 ADC Output Register (read-only): The 16-bit twos complement values read from this register are the output of the AD28msp01's analog-to-digital converter. Data Register 3 address = 0x09 Interpolation Filter Output Register (read-only): The 16-bit twos complement values read from this register are the output of the resampling interpolation filter. Addresses 0x0A--0x1F are reserved. Table II contains the register addresses.
Table II. Register Addresses
Transferring the following 16-bit words to the AD28msp01 will initialize Control Registers 0-3. Word Transferred 0x0000 0x0254 0x0002 0x0031 0x0003 0x0032 0x0001 0x0018 Description Control Register 0 Address Word Write this value to Control Register 0 Control Register 2 Address Word Write this value to Control Register 2 Control Register 3 Address Word Write this value to Control Register 3 Control Register 1 Address Word Write this value to Control Register 1
Note that in this example the power-down bits in Control Register 1 are released (set to 1) only after the AD28msp01 is fully configured by writing to Control Registers 0, 2, and 3.
Transferring Data from the AD28msp01 to the Host
Address Bits 4-0 Register 00000
Description
00001
00010 00011 00100 00101 00110 00111 01000 01001 01010 .... .... 11111
Control Register 0 Data rate and synchronization rate selects, interpolation filter enable Control Register 1 Filter bypass, test, power-down mode bits, V.32ter mode select bits Control Register 2 ADC bit and baud rate selects Control Register 3 DAC bit and baud rate selects Control Register 4 Receive phase adjust Control Register 5 Transmit phase adjust Data Register 0 DAC input register Data Register 1 Interpolation filter input register Data Register 2 ADC output register Data Register 3 Interpolation filter output register Reserved ........ ........ Reserved
Data transfers to the host processor can only be initiated by the AD28msp01. When transferring data the AD28msp01 first specifies the source register by transferring a 16-bit address word and then transfers the contents of the source register. Bits 5-14 of the address word will always be forced to zero. When transferring data, the serial data stream from the AD28msp01 will consist of a sequence of alternating address and data words.
Transferring Control Words from the AD28msp01 to the Host
All control registers in the AD28msp01 are host-readable. To read a control register, the host must transmit a 16-bit address word with the Read/ Write bit set, then transmit a dummy data word. The AD28msp01 will respond by first completing any AD28msp01-to-Host transfer in progress. As soon as the dummy data word is received, the device will transfer a 16-bit word with the control register address and then transmit the contents of the control register.
Example
The following data streams show how a host can read the contents of an AD28msp01 control register: Host Transfer 0x8001 0x1234 0x 0x 0x0001 0x0023
Serial Port Timing
AD28msp01 Transfer
Description Read Control Register 1 Dummy data word AD28msp01 completes data Transfer in progress Address word Contents of Control Register 1
Transferring Data and Control Words to the AD28msp01
Data and control word transfers to the AD28msp01 can only be initiated by the host processor. When transferring data to the AD28msp01, the host processor specifies the destination register by first transmitting a 16-bit address word (Figure 6) and then transmitting the 16-bit data word. The read/write bit in the address word must be deasserted. The serial data stream from the host processor will consist of a sequence of alternating address and data words. The AD28msp01 will not write the target register until both the address word and data word are completely transferred.
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
All serial transfers are synchronous. The receive data (SDI) and receive frame sync (SDIFS) are clocked into the device on the falling edge of SCLK. The receive frame sync (SDIFS) must be asserted one SCLK cycle before the first data bit is transferred. When receiving data, the AD28msp01 ignores the receive frame sync pin until the least significant bit is being received. When transmitting data, the AD28msp01 asserts transmit frame sync (SDOFS) and transmit data (SDO) synchronous with the rising edge of SCLK. Transmit frame sync is transmitted one SCLK cycle before the first data bit is transferred.
Operating Modes
READ/WRITE 1 = read 0 = write
Address bits [4...0] See Table I.
Figure 6. Address Word
The AD28msp01 is capable of operating in several different modes, as described below. -10- REV. A
AD28msp01
V.32 TSYNC Mode
In V.32 TSYNC Mode, shown in Figure 7, the AD28msp01's transmit circuitry is synchronized to an external TSYNC signal. The AD28msp01 receive circuitry is sampled synchronous to the transmit circuitry, but the data can be resampled at a different phase by using the resampling interpolation filter. TCONV, TBIT and TBAUD are generated internally but are phase-locked to the external TSYNC input signal with the digital phase-locked loop. RCONV, RBIT and RBAUD are generated internally (but frequency locked to TSYNC) and can be phase adjusted with the Receive Phase Adjust Register (Control Register 4). TCONV initiates a new DAC sample update, loads the ADC register (Data Register 2), and loads the DAC register (Data Register 0) with a new sample. The digital resampling interpolation filter can be used for digital resampling of the received signal. Enable this function by setting Bit 9 in Control Register 0. The phase of the resampled signal is adjusted with the Receive Phase Adjust Register. Samples are loaded into the interpolator at the TCONV rate and are resampled at the RCONV rate. When entering V.32 TSYNC Mode, RCONV is locked to TCONV before TCONV is locked to TSYNC. If this mode is entered from a non-V.32 mode, the device performs a soft reset. The time required to lock TCONV to RCONV is dependent on the phase difference between RCONV and TCONV when entering the mode.
This mode is entered by setting the Operating Mode field in Control Register 0. The RCONV/TCONV rate can be set to 9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The TBIT and TBAUD clock rates are set by adjusting the appropriate bits in Control Register 3. The RBIT and RBAUD clock rates are set by adjusting the appropriate bits in Control Register 2. The bit rates, baud rates and TSYNC rate can be set to any combination of clock rates listed in the control register descriptions. The TSYNC field on Control Register 0 must be set to the frequency of the input pin.
Example
Transferring the following word sequence to the AD28msp01 will configure the device for V.32 TSYNC Mode at the clock rates indicated: Word Transferred 0x0000 0x0254 0x0002 0x0002 0x0003 0x0023 0x0001 0x0018 Description Control Register 0 address word Enable interpolation filter, TSYNC = 7200, sample rate = 7200, mode = V.32 TSYNC Control Register 2 address word RBAUD = 2400, RBIT = 7200 Control Register 3 address word TBAUD = 1200, TBIT = 4800 Control Register 1 address word Configure and power-up device
ANALOG IN
A/D
16
AD28msp01
DATA REGISTER 2 RX CLOCKS RX CLOCKS 16 INTERPOLATION FILTER DATA REGISTER 1 16 PHASE ADJUST CONTROL REGISTER 4 RX PHASE ADJUST 16 DATA REGISTER 3 16 16
DSP Processor
TX CLOCKS TCONV TBIT TBAUD PHASE ADJUST MCLK DIGITAL PHASE LOCKED LOOP CONVERT START
RCONV RBIT RBAUD PHASE ADJUST
ECHO CANCELLATION
TSYNC
TO MODEM RX
ANALOG OUT
D/A
16
DATA REGISTER 0
16 FROM MODEM TX
Figure 7. V.32 TSYNC Mode Block Diagram
REV. A
-11-
AD28msp01
V.32 Internal Sync Mode
In V.32 Internal Sync Mode, shown in Figure 8, the AD28msp01's transmit clocks are generated internally. The receive circuitry operates synchronous to the transmit circuitry, but the data can be resampled at a different phase through the resampling interpolation filter. TCONV, TBIT and TBAUD are generated internally and can be phase adjusted with the Transmit Phase Adjust Register (Control Register 5). RCONV, RBIT and RBAUD are also generated internally and can be phase adjusted with the Receive Phase Adjust Register (Control Register 4). TCONV initiates a new ADC sample update, loads the ADC register (Data Register 2), and loads the DAC register (Data Register 0) with a new sample. The digital resampling interpolation filter can be used for digital resampling of the received signal. Enable this function by setting Bit 9 in Control Register 0. The phase of the resampled signal is
adjusted with the Receive Phase Adjust Register. Samples are loaded into the interpolator at the TCONV rate and are resampled at the RCONV rate. When entering V.32 Internal Sync Mode, RCONV is first locked to TCONV. RCONV is then phase adjusted whenever a new value is written to the Receive Phase Adjust Register (Control Register 4). If this mode is entered from a non-V.32 mode, the device performs a soft reset. The time required to lock TCONV to RCONV is dependent on the phase difference between RCONV and TCONV when entering the mode. This mode is entered by setting the Operating Mode field in Control Register 0. The RCONV/TCONV rate can be set to 9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The TBIT and TBAUD clock rates are set by adjusting the appropriate bits in Control Register 3. The RBIT and RBAUD clock rates are set by adjusting the appropriate bits in Control Register 2. The bit and baud rates can be set to any combination of clock rates listed in the control register descriptions.
AD28msp01
ANALOG IN A/D 16 DATA REGISTER 2 RX CLOCKS RX CLOCKS TX CLOCKS TCONV TBIT TBAUD PHASE ADJUST MCLK CONTROL REGISTER 5 TX PHASE ADJUST CONTROL REGISTER 4 RX PHASE ADJUST CONVERT START RCONV RBIT RBAUD PHASE ADJUST 16 INTERPOLATION FILTER DATA REGISTER 1 16 PHASE ADJUST 16 DATA REGISTER 3 16 16
DSP Processor
ECHO CANCELLATION
TO MODEM RX
ANALOG OUT
D/A
16
DATA REGISTER 0
16 FROM MODEM TX
Figure 8. V.32 Internal Sync Mode Block Diagram
-12-
REV. A
AD28msp01
V.32 Loopback Mode
In V.32 Loopback Mode, shown in Figure 9, the AD28msp01's receive circuitry and transmit circuitry are locked together. RCONV is generated internally and can be phase adjusted with the Receive Phase Adjust Register (Control Register 4). RBIT, RBAUD, TCONV, TBIT and TBAUD are all locked to RCONV.
RCONV initiates a new DAC sample update and loads Data Register 2 with a new sample. The RCONV rate can be set to 9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The bit and baud rates can be set to any combination of clock rates listed in the control register descriptions.
AD28msp01
ANALOG IN A/D 16 DATA REGISTER 2 16
DSP Processor
TX CLOCKS RX CLOCKS RCONV RBIT RBAUD PHASE ADJUST MCLK TX CLOCKS TCONV TBIT TBAUD PHASE ADJUST CONVERT START CONTROL REGISTER 4 RX PHASE ADJUST
ANALOG OUT
D/A
16
DATA REGISTER 0
Figure 9. Loopback Mode Block Diagram
V.32ter TSYNC Mode V.32ter Internal Sync Mode
This mode is identical to V.32 TSYNC Mode except all clocks are scaled by a factor of 8/7 over the corresponding V.32 TSYNC rate. In this mode, the maximum value to which the receive and transmit phase adjust registers (Control Registers 4 and 5) may be set is +192. Both TBIT and RBIT can be set to a 19,200 Hz rate that will not be scaled by a factor of 8/7, by setting the appropriate fields in Control Registers 2 and 3.
This mode is identical to V.32 TSYNC Mode except all clocks are scaled by a factor of 8/7 over the corresponding V.32 TSYNC rate. In this mode, the maximum value to which the phase adjust registers (Control Registers 4 and 5) may be set is +192. Both TBIT and RBIT can be set to a 19,200 Hz rate that will not be scaled by a factor of 8/7, by setting the appropriate fields in Control Registers 2 and 3.
REV. A
-13-
AD28msp01
Asynchronous Fallback TSYNC Mode
The Asynchronous Fallback TSYNC Mode is shown in Figure 10. TCONV, TBIT and TBAUD are generated internally but phase locked to the external TSYNC input signal. RCONV, RBIT and RBAUD are generated internally and can be phase adjusted with the Receive Phase Adjust Register (Control Register 4). This mode is entered by setting the Operating Mode field in Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The TBIT and TBAUD clock rates are set by adjusting the appropriate bits in Control Register 3. The RBIT and RBAUD clock rates are set by adjusting the appropriate bits in Control Register 2. The bit rates, baud rates and TSYNC rate can be set to any combination of clock rates listed in the control register descriptions.
AD28msp01
ANALOG IN A/D 16 DATA REGISTER 2 16
DSP Processor
TO MODEM RX
TX CLOCKS RX CLOCKS RCONV RBIT RBAUD PHASE ADJUST MCLK TX CLOCKS TCONV TBIT TBAUD PHASE ADJUST
CONVERT START
CONTROL REGISTER 4 RX PHASE ADJUST
TSYNC
DIGITAL PHASE LOCKED LOOP
ANALOG OUT
D/A
16
DATA REGISTER 0
16
FROM MODEM TX
Figure 10. Asynchronous Fallback TSYNC Driven Mode Block Diagram
Asynchronous Fallback Mode
The Asynchronous Fallback Mode is shown in Figure 11. TCONV, TBIT and TBAUD are generated internally and can be phase adjusted with the Transmit Phase Adjust Register (Control Register 5). RCONV, RBIT and RBAUD are generated internally and can also be phase adjusted with the Receive Phase Adjust Register (Control Register 4). The digital phaselocked is not used in this operating mode.
This mode is entered by setting the Operating Mode field in Control Register 0. The RCONV/TCONV rate can be set to 9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field in Control Register 0. The TBIT and TBAUD clock rates are set by adjusting the appropriate bits in Control Register 3. The RBIT and RBAUD clock rates are set by adjusting the appropriate bits in Control Register 2. The bit and baud rates can be set to any combination of clock rates listed in the control register descriptions.
-14-
REV. A
AD28msp01
AD28msp01
ANALOG IN A/D 16 DATA REGISTER 2 16
DSP Processor
TO MODEM RX
TX CLOCKS RX CLOCKS RCONV RBIT RBAUD PHASE ADJUST MCLK TX CLOCKS TCONV TBIT TBAUD PHASE ADJUST
CONVERT START
CONTROL REGISTER 4 RX PHASE ADJUST
CONVERT START CONTROL REGISTER 5 TX PHASE ADJUST DATA REGISTER 0 16
ANALOG OUT
D/A
16
FROM MODEM TX
Figure 11. Asynchronous Fallback Mode Block Diagram
Operating Mode Summary
Table III summarizes the operating modes.
Table III. Operating Mode Summary
Mode Async Fallback Async TSYNC V.32 TSYNC
Initial Phase Phase Adjust Lock After Normal DPLL* Register Resampling Entering Mode Operation Programmable Interpolator no phase lock TCONV lock to TSYNC RCONV lock to TCONV no phase lock TCONV lock to TSYNC TCONV lock to TSYNC RCV, TX RCV RCV not used not used
Internal Filter Operation Synchronous To: ADC DAC RCONV RCONV
Control Register 0 OP 2-0
TCONV 0 0 0 TCONV 1 1 1 TCONV 1 0 0
Input synchronous TCONV and in phase with TCONV, Output synchronous and in phase with RCONV Input synchronous TCONV and in phase with TCONV, Output synchronous and in phase with RCONV not used TCONV
V.32 Internal Sync RCONV lock to TCONV
no phase lock
RCV, TX
TCONV 1 0 1
V.32 Loopback
TCONV lock to RCONV
no phase lock
RCV
TCONV 1 1 0
NOTES *DPLL--Digital Phase-Locked loop. RCV phase adjusted via Control Register 4, TX phase adjusted via Control Register 5. Adjusting RCV phase also adjusts TX phase in this mode. Note: All receive clocks: RBIT, RBAUD are synchronous to RCONV. All transmit clocks: TBIT, TBAUD are synchronous to TCONV.
REV. A
-15-
AD28msp01
DESIGN CONSIDERATIONS Analog Input
The analog input signal to the AD28msp01 must be ac coupled. Figure 12 shows the recommended input circuit for the AD28msp01's analog input pin (VIN). The circuit of Figure 12 implements a first-order low-pass filter with a 3 dB point at 20 kHz; this is the only filter that must be implemented external to the AD28msp01 to prevent aliasing of the sampled signal. Since the AD28msp01's ADC uses a highly oversampled approach that transfers the bulk of the anti-aliasing filtering into the digital domain, the off-chip anti-aliasing filter need only be of low order. In the circuit shown in Figure 12, scaling of the analog input is achieved by the resistors RIN and RFB. The input signal gain, -RFB/RIN, can be adjusted by varying the values of these resistors. Total gain must be configured to ensure that a full-scale input signal (at CIN in Figure 12) produces a signal level at the input to the sigma-delta modulator of the ADC that does not exceed VINMAX, which is specified under "Analog Interface Electrical Characteristics." If the total gain is increased above unity (i.e., gain >1), signal-to-noise (SNR + THD) performance may not meet the listed specifications. The dc offsetting of the analog input signal is accomplished with an on-chip voltage reference which nominally equals 2.5 V. The input signal must be ac coupled with an external coupling capacitor (CIN). CIN and RIN should be chosen to ensure a coupling corner frequency of 30 Hz. CIN should be 0.1 F or larger.
CFB VFB CIN INPUT SIGNAL RIN RFB VIN
Figure 13 shows an example of a typical input circuit configured for 0 dB gain. The circuit's diodes are used to prevent the input signal from exceeding maximum limits.
330pF VCC VFB 10k INPUT SIGNAL 1.0F 10k 20k VIN
GNDA
VOLTAGE REFERENCE
AD28msp01
Figure 13. Typical Input Circuit (0 dB Gain)
Analog Output
The AD28msp01's differential analog output (VOUTP, VOUTN) is produced by an on-chip differential amplifier. The differential amplifier can drive a minimum load of 2 k (RL 2 k) and has a maximum differential output voltage swing of 6.312 V peak-to-peak (3.17 dBm0). The differential output can be accoupled directly to a load or dc-coupled to an external amplifier.
AD28msp01
COUT VOUTP RL COUT
VOLTAGE REFERENCE
VOUTN
AD28msp01
Figure 14. Example Circuit for Differential Output with AC Coupling
Figure 12. Recommended Analog Input Circuit
To select values for the components shown in Figure 12, use the following equations:
Figure 14 shows a simple circuit providing a differential output with ac coupling. The capacitor of this circuit (COUT) is optional; if used, its value can be chosen as follows: COUT = 1 (60 ) RL
Gain = CIN = C FB =
- RFB RIN 1
60 RIN 1
3
The VOUTP-VOUTN outputs must be used as differential outputs; do not use either as a single-ended output. Figure 15 shows an example circuit which can he used to convert the differential output to a single-ended output. The circuit uses a differentialto-single-ended amplifier, the Analog Devices SSM2141.
(2 )(20 *10 ) RFB
10 k RFB, RIN 50 k 150 pF CFB 600 pF
-16-
REV. A
AD28msp01
DEFINITION OF SPECIFICATIONS
+12V 0.1F GNDA 7 5 VOUT SSM2141 SSM-214 1 4 GNDA 0.1F GNDA -12V VOUTN VOUTP
AD28msp01
Typical (Typ) specifications represent nominal performance at +25C with VCC and VDD set to +5 V. Minimum (Min) and Maximum (Max) specifications are guaranteed across the full operating range, however, devices are tested only at the indicated test conditions.
Absolute Gain
Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured with a 1.0 kHz sine wave at 0 dBm0. The absolute gain specification is used as a reference for gain tracking error specification.
Gain Tracking Error
Figure 15. Example Circuit for Single-Ended Output
Single Power Supply Operation
Gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. The absolute signal level is 1 kHz at 0 dBm0 (equal to absolute gain). Gain tracking error at 0 dBm0 is 0 dB by definition.
SNR
Use of a single +5 V power supply is possible with the AD28msp01. If a single supply is used, the analog power supply input to the device must be properly filtered. The proper filter is dependent on the noise present in your system.
PC Board Layout Considerations
Signal-to-noise ratio is defined to be the ratio of the rms value of the measured input signal to the rms sum of all the spectral components in the specified passband, excluding dc and harmonic components.
THD
Separate analog and digital ground planes should be provided for the AD28msp01 in order to assure the characteristics of the device's ADC and DAC. The two ground planes should be connected only at a single point. The point of connection may be at the system power supply, at the PC board power connection, or at any other appropriate location. Multiple connections between the analog and digital ground planes should be avoided. The ground planes should be designed such that all noisesensitive areas are isolated from one another and critical signal traces (such as digital clocks and analog signals) are as short as possible. Each +5 V supply pin of the AD28msp01 should be bypassed to ground with a 0.1 F capacitor. These capacitors should be low inductance, monolithic, ceramic, and surface-mount. The capacitor leads and PC board traces should be as short as possible to minimize inductive effects. In addition, a 10 F capacitor should be connected between VDD and ground, near the PC board power connection.
MCLK Frequency
Total harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of the harmonic components in the specified passband.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. This specification contains the second order terms include (fa + fb) and (fa - fb), and the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb).
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured at the output of the device when the input is grounded (measured in the specified passband).
Crosstalk
The sigma-delta converters and digital filters of the AD28msp01 are specifically designed to operate at a master clock (MCLK) frequency of 13.824 MHz. MCLK must equal 13.824 MHz to guarantee the filter characteristics and sample rate of the ADC and DAC. The AD28msp01 is not tested or characterized at any other clock frequency.
Crosstalk is defined as the ratio of the amplitude of a 0 dB signal appearing on one channel to the amplitude of the same signal coupled onto the other, idle channel. Crosstalk is expressed in dB.
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to noise on the power supply. Power supply rejection is measured by modulating the power supply with a 1 kHz, 100 mV p-p sine wave and measuring the relative level at the output.
Group Delay
Group delay is defined as the derivative of radian phase with respect to radian frequency, ()/. Group delay is a measure of the linearity of the phase response of a linear system. A linear system with a constant group delay has a linear phase response. The deviation of the group delay away from a constant indicates the degree of nonlinear phase response of the system.
REV. A
-17-
AD28msp01-SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade Symbol VDD, VCC TAMB Parameter Supply Voltage Ambient Operating Temperature Min 4.75 0 Max 5.25 +70 Unit V C
Refer to Environmental Conditions for information on case temperature and thermal specifications.
ABSOLUTE MAXIMUM RATINGS*
Test Conditions Unless Otherwise Noted
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . . . 0C to +70C Storage Temperature Range . . . . . . . . . . . . -55C to +150C Lead Temperature (5 seconds) SOIC . . . . . . . . . . . . +280C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature Sample Rate (FS) Input Signal Frequency Input Signal Level Analog Input Gain Analog Output Passband
+25C 9.6 kHz 993.75 Hz 0.0 dBm0 Unity 220 Hz to 3.4 kHz
ESD SENSITIVITY The AD28msp01 features proprietary input protection circuitry to dissipate high-energy discharges (Human Body Model). Per Method 3015 of MIL-STD-883 the AD28msp01 has been classified as a Class 1 device. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam, trays, or tubes, and the foam should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
-18-
REV. A
AD28msp01
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH VOL IIH IIL IOZL IOZH CI
1
Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage High Level Input Current Low Level Input Current Low Level Output 3-State Leakage Current High Level Output 3-State Leakage Current Digital Input Capacitance1
Min 2.4
Typ
Max 0.8
Unit V V V V A A A A pF
Test Condition VDD = max VDD = min VDD = min, IOH = -0.5 mA VDD = min, IOL = 2 mA VDD = max, VIN = max VDD = max, VIN = 0 V VDD = max, VIN = max VDD = max, VIN = 0 V
2.4 0.4 10 10 10 10 10
Guaranteed but not tested.
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
Symbol ADC: IL RI CIL VINMAX DAC: Ro VOFF COL VO RL
Parameter Input Leakage Current at VIN Input Resistance at VIN Input Load Capacitance at VFB Maximum Input Range1 Output Resistance Output DC Offset2 Output Load Capacitance Maximum Voltage Output Swing (p-p) Across RL Single-Ended Differential Load Resistance
Min
Typ 10 100 10 3.156 1
Max
Unit nA M pF V p-p mV pF V V k
-400
400 100 3.156 6.312
2
Test Conditions for all analog interface tests: Unity input gain, no load on analog output (VOUTP-VOUTN). 1 At unity gain on input. 2 Between V OUTP and VOUTN.
POWER DISSIPATION
Symbol VCC VDD ICC IDD P1 ICC IDD P0
Parameter Analog Operating Voltage Digital Operating Voltage Analog Operating Current Active1 Digital Operating Current Active1 Power Dissipation Active' Analog Operating Current Inactive2 Digital Operating Current Inactive2 Power Dissipation Inactive2
Min 4.75 4.75
Typ 5.0 5.0 24 11
Max 5.25 5.25 35 20 350 300 200 4.0
Unit V V mA mA mW A A mW
Test conditions: VDD = VCC = 5.0 V, MCLK frequency 13.824 MHz, no load on digital pins, analog inputs ac-coupled to ground, no load on analog output (VOUTP-VOUTN). 1 Active: AD28msp01 operational (PWDD and PWDA set to 1 in Control Register 1). 2 Inactive: AD28msp01 in power-down state (PWDD and PWDA set to 0 in Control Register 1) and MCLK tied to VDD.
REV. A
-19-
AD28msp01
TIMING PARAMETERS
Parameter Clock Signals Timing Requirement: FMCK tMCK tMKL tMKH Switching Characteristic: tSCK tSKL tSKH Control Signals Timing Requirement: tRSP RESET Width Low MCLK Frequency MCLK Period MCLK Width Low MCLK Width High SCLK Period SCLK Width Low SCLK Width High
Min
Max
Unit
13.824 72.34 0.5tMCK - 10 0.5tMCK - 10 8tMCK - 10 4tMCK - 10 4tMCK - 10
13.824 72.34 0.5tMCK + 10 0.5tMCK + 10 8tMCK + 10 4tMCK + 10 4tMCK + 10
MHz 50 ppm ns ns ns ns ns ns
5tMCK1
ns
NOTE 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 1000 processor cycles assuming stable CLKIN (not including crystal oscillator start-up time).
tMCK
MCLK
tMKL
tMKH
tSCK
SCLK
tSKL
tSKH
Figure 16. Clock Signals
Serial Port 3-State Parameter Switching Characteristic: tSPD tSPE tSPV CS Low to SDO, SDOFS, SCLK Disable CS High to SDO, SDOFS, SCLK Enable CS High to SDO, SDOFS, SCLK Valid Min Max 20 0 25 Unit ns ns ns
tSPD
CS
tSPV
tSPE
SDO SDOFS SCLK
Figure 17. Serial Port 3-State
-20-
REV. A
AD28msp01
Output Disable Time Output Enable Time
Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high-impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time, tMEASURED, is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: t DECAY = from which tDIS = tMEASURED - tDECAY is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving.
Serial Ports
Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
REFERENCE SIGNAL
t MEASURED
CL x 0.5 V iL
t DIS
V V (MEASURED) OUTPUT (MEASURED)
t ENA
VOH (MEASURED) - 0.5V V OL(MEASURED) + 0.5V 2.0V 1.0V VOH (MEASURED) VOL (MEASURED)
OH
OL
t DECAY
OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5 V.
Figure 18. Output Enable/Disable
Parameter Timing Requirement: tSCS tSCH Switching Characteristic: tRD tRH tSCDH tSCDD SDI/SDIFS Setup before SCLK Low SDI/SDIFS Hold after SCLK Low SDOFS Delay from SCLK High SDOFS Hold after SCLK High SDO Hold after SCLK High SDO Delay from SCLK High
Min
Max
Unit
10 15 30 0 0 30
ns ns ns ns ns ns
tSCK
SCLK
tSCS
SDIFS
tSCH
tSCH
MSB 2ND MSB 3RD MSB
SDI
tSCS tRD
SDOFS
tRH tSCDD
SDO
tSCDH
Figure 19. Serial Ports
REV. A
-21-
AD28msp01
DIGITAL TEST CONDITIONS
3.0V 1.5V 0.0V
IOL
DIGITAL INPUT
DIGITAL OUTPUT
2.0V 1.5V 0.8V
TO DIGITAL OUTPUT PIN 50pF
+1.5V
Figure 20. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
IOH
Figure 21. Equivalent Device Loading for AC Measurements (Includes ALI Fixtures)
GAIN
Parameter ADC Absolute Gain ADC Gain Tracking Error DAC Absolute Gain DAC Gain Tracking Error
Min -0.5 -0.1 -0.5 -0.1
Typ 0 0 0 0
Max 0.5 0.1 0.5 0.1
Unit dBm0 dBm0 dBm0 dBm0
Test Conditions 1.0 kHz, 0 dBm0 1.0 kHz, +3 and -60 dBm0 1.0 kHz, 0 dBm0 1.0 kHz, +3 and -60 dBm0
FREQUENCY RESPONSE*
ADC Passband Ripple Low-Pass Passband Cutoff Frequency Low-Pass Stopband Cutoff Frequency High-Pass Passband Cutoff Frequency High-Pass Stopband Cutoff Frequency Low-Pass Stopband Rejection High-Pass Stopband Rejection DAC Passband Ripple Passband Cutoff Frequency Low-Pass Stopband Cutoff Frequency Stopband Rejection
*Frequency Response is guaranteed but not tested.
9.6 kHz <0.2 dB 3.4 kHz 4.8 kHz 220 Hz 60 Hz -50 dB -50 dB 9.6 kHz <0.2 dB 3.4 kHz 4.8 kHz -50 dB
8.0 kHz <0.2 dB 3.4 kHz 4.0 kHz 220 Hz 60 Hz -50 dB -50 dB 8.0 kHz <0.2 dB 3.4 kHz 4.0 kHz -50 dB
7.2 kHz <0.2 dB 3.3 kHz 3.6 kHz 220 Hz 60 Hz -50 dB -50 dB 7.2 kHz <0.2 dB 3.4 kHz 3.6 kHz -50 dB
-22-
REV. A
AD28msp01
NOISE AND DISTORTION
Parameter ADC Signal-to-Noise Ratio ADC Total Harmonic Distortion DAC Signal-to-Noise Ratio DAC Total Harmonic Distortion ADC Idle Channel Noise DAC Idle Channel Noise ADC Crosstalk1 DAC Crosstalk ADC Intermodulation Distortion1 DAC Intermodulation Distortion1 ADC Digital Power Supply Rejection DAC Digital Power Supply Rejection1 ADC Analog Power Supply Rejection1 DAC Analog Power Supply Rejection1
1
Min +72 +72
Typ +80
Max -72
Unit dB dB dB dB dBm0 dBm0 dB dB dB dB dB dB dB dB
+80 -72 -80 -80 -72 -72 -72 -72 -72
1
1
-45 -45 -35 -35
Guaranteed but not tested
80 70 60 50
SNR - dB
17dB
40 30 20 10 0
-10 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 VIN - dBm0
0 3.17
Figure 22. Typical SNR vs. VIN
GROUP DELAY*
9.6 kHz ADC Group Delay ADC Low-Pass Filter Group Delay ADC High-Pass Filter Group Delay DAC Group Delay Resampling Filter Group Delay
*Group Delay is guaranteed but not tested.
8.0 kHz 13 3 10 3 3
7.2 kHz 15 5 10 5 5
Unit ms ms ms ms ms
12 2 10 2 2
REV. A
-23-
AD28msp01
PIN CONFIGURATIONS 28-Pin DIP and 28-Lead SOIC
VCC VCC 1 2 28 27 26 25 24 23 NC VIN VFB GNDA GNDD CS SDI
VOUTP 3 VOUTN 4 NC GNDA GNDA GNDD GNDD RESET NC TSYNC TCONV NC 5 6 7 8 9 10 11 12 13 14
AD28msp01
TOP VIEW (Not to Scale)
22
21 SDIFS 20 19 18 SDOFS SDO SCLK
17 V DD 16 VDD 15 GNDD
NC = NO CONNECT
44-Lead Plastic Leaded Chip Carrier (PLCC)
VOUTN VOUTP GNDA VCC NC GNDA
40
VCC
VFB
42
VIN
6
5
4
3
2
1
44
NC
43
41
GNDA GNDD GNDD RESET NC TSYNC TCONV NC TBIT TBAUD NC
NC
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
39 38 37 36
GNDA GNDD GNDD CS NC SDI SDIFS NC SDOFS SDO NC
AD28msp01
TOP VIEW (Not to Scale)
35 34 33 32 31 30 29
RBIT
RCONV
RBAUD
MCLK
GNDD
GNDD
NC = NO CONNECT
SCLK
VDD
VDD
VDD
NC
-24-
REV. A
AD28msp01
44-Lead Thin Quad Flat Pack
GNDA NC VOUTN VOUTP VCC VCC NC VIN VFB NC GNDA
44 1 34 33
GNDA GNDD GNDD RESET NC TSYNC TCONV NC TBIT TBAUD NC
11 12 22
TOP VIEW (Pins Down)
GNDA GNDD GNDD CS NC SDI SDIFS NC SDOFS SDO NC
23
NC = NO CONNECT
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
1.450 (36.830) 1.440 (35.580)
28 15
1
PIN 1
RCONV RBIT RBAUD MCLK GNDD GNDD VDD VDD VDD NC SCLK
N-28 28-Pin Plastic DIP
0.550 (13.970) 0.530 (13.470)
14
0.060 (1.580) 0.020 (0.508)
0.606 (15.400) 0.594 (15.090)
0.200 (5.080) MAX SEATING PLANE 0.020 (0.508) 0.015 (0.381)
0.175 (4.450) 0.120 (3.050) 0.105 (2.670) 0.096 (2.420) 15 0 0.012 (0.306) 0.008 (0.203)
REV. A
-25-
AD28msp01
P-44A 44-Lead Plastic Leaded Chip Carrier (PLCC)
0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
6 7 PIN 1 IDENTIFIER
0.056 (1.42) 0.042 (1.07)
40 39
0.025 (0.63) 0.015 (0.38)
0.050 (1.27) BSC
0.63 (16.00) 0.59 (14.99)
TOP VIEW
(PINS DOWN)
0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
17 18
29 28
0.020 (0.50) R
0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40)
R-28 28-Lead Wide-Body SOIC
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
SEATING 0.0125 (0.32) PLANE 0.0091 (0.23)
8 0
0.0500 (1.27) 0.0157 (0.40)
-26-
REV. A
AD28msp01
ST-44 44-Lead Metric Thin Plastic Quad Flat Pack (TQFP)
0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.549 (13.95) 0.397 (10.07) 0.391 (9.93)
44 1 34 33
0.063 (1.60) MAX 0.030 (0.75) 0.019 (0.50) SEATING PLANE
TOP VIEW
(PINS DOWN)
0.004 (0.10) MAX 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
11 12 22
23
0.042 (1.07) 0.037 (0.93)
0.016 (0.40) 0.012 (0.30)
ORDERING GUIDE
Part Number AD28msp01KP AD28msp01KN AD28msp01KR AD28MSP01KST
Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C
Package 44-Pin PLCC 28-Pin Plastic DIP 28-Lead SOIC 44-Lead TQFP
0.397 (10.07) 0.391 (9.93) 0.553 (14.05) 0.549 (13.95 0.640 (16.25) 0.620 (15.75)
Package Option* P-44A N-28 R-28 ST-44
NOTES *P = PLCC, N = Plastic DIP, R = Small Outline (SOIC), ST = TQFP. In Development.
REV. A
-27-
-28-
C1726a-4-8/93
PRINTED IN U.S.A.

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